1. Field of the Invention
The present invention generally relates to testers for very Large Scale Integrated (VLSI) circuits and, more particularly, is concerned with a VLSI tester backplane that facilitates the insertion, connection, inspection, test, and removal of a plurality of pin electronics (PE) boards, and a device-under-test (DUT) board, in a design verification system.
2. Description of the Prior Art
A chip is the smallest unit of fabrication in semiconductor technologies. A single chip normally will contain multiple transistors that are connected into more useful entities known as logic gates. Complex chips have many logic gates, forming multiple logic circuits. VLSI chips, a class of chips with exceedingly dense circuitry, can host as many as 10 million transistors per chip, and can embody a number of computational devices on a single chip, including memories and microprocessors.
As presently fabricated, a chip is a thin (0.2 to 0.25 mm) piece of square or rectangular silicon encapsulated in an outer package. This package, for example, a dual inline package (DIP), provides pins that electrically connect the chip to its operating environment, normally a printed circuit board. The pieces of silicon are generally first fabricated as a matrix of dozens or even hundreds of dies that are etched on a large slice of silicon, termed a wafer. After fabrication, the wafer is cut up and the individual dies are packaged into chips. Each die, while still on the wafer, includes electrical contacts that allow electrical signals to be input and output from the die circuitry.
As can be easily imagined, VLSI chips must be tested both during the prototype stages of development and thereafter during mass production, to verify first the integrity of their design, and then the quality of their manufacture. Testing can be performed either prior to or after packaging. Design verification systems have been developed that selectively excite the inputs of an integrated circuit chip with many input combinations, called test vectors. Nearly simultaneously, the outputs of the chip are checked for accuracy. For every test vector, there is an expected output, which is defined by the function performed by the electronic circuitry located within the chip. If there is a discrepancy between the expected output and the actual output when the circuit is presented with a specific test vector, there is likely a design error or, later, a manufacturing error in the chip By testing a large number of input combinations, the likelihood that a design or manufacturing fault in the chip will pass undetected is significantly reduced, if not eliminated.
A typical design verifier used to test prototype chips includes a metallic chassis that holds the electronic circuitry necessary to test a chip, termed the device-under-test (DUT). The circuitry undergoing testing is typically mounted on a printed circuit board that electromechanically positions the integrated circuit device such that the pins of the chip can be connected to the test circuitry in the chassis. This circuit board, generally known as a DUT board, also functions to maintain a controlled impedance signal path from the test electronics to the chip pins. This is normally accomplished by providing paths of near equal length for electrical signal travel. The DUT board is also normally removable, so that removable connecting wires can be easily placed between the chip pins in the center of the board and the input/output (I/O) stimulus connections on the periphery of the board.
The I/O stimulus connections on the DUT board are sometimes connected to the electronics of the testing circuitry by raised pins located on a test platform, (which is frequently referred to as load board), that is located on an outer surface of the chassis. For example, the invention disclosed by Schwar, et al., (U.S. Pat. No. 4,782,289) is illustrative of such a load board. The load board is securely fastened to the chassis, and supports the DUT board when it is in place on the design verifier. The load board also functions as a backplane, channeling electrical test signals and power from the underlying pin electronics (PE) boards to the DUT board.
The PE boards carry the test electronics circuitry used to stimulate the DUT, and then to compare the actual resultant signals with expected results. Pin driver circuits supply the proper voltages and timing for the DUT pins, and compensate for signal distortion and noise disturbances. The proper driver information, such as voltage level, is encoded as digital test vectors stored in random access memory (RAM) on the PE boards. The PE boards further contain receivers and output comparators. The pin outputs are thereby received and compared against the expected outputs stored in RAM. The PE boards are typically connected to the load board using edge connectors located on the PE boards and fitting them into edge connector receptacles located on the load board.
In some design verifiers a provision is made to allow the verifier to be connected directly to a die held in a wafer prober. A wafer prober is a device that accurately positions wafer dies such that I/O contacts on the die are accessible for probing. A typical wafer prober comes with a microscope to allow an operator to connect a DUT board to the wafer at the desired die contacts through a connecting or top hat assembly. If a design verifier is mated with a wafer prober, then testing can be performed on the chip prior to encapsulation, thus saving large amounts of time and expense.
Mating a design verifier and a wafer prober is accomplished by placing the design verifier, typically a large and heavy machine, on a manipulator. A manipulator is a crane-like device used to hoist and position the heavy and bulky verifier chassis filled with electronics. The manipulator allows a special wafer prober DUT board to be positioned adjacent to a wafer prober and locked thereto with a docking plate.
There are at least two accepted mechanisms known in the prior art for arranging the entire set of abovementioned boards in a design verifier chassis. In the first, the DUT board is clamped to the load board with a plurality of PE boards within the chassis and underlying the load board. Thumbscrews located about the periphery of the DUT board are typically screwed through the DUT board and into a number of threaded bores formed in the load board to hold the DUT board stationary. The second arrangement of verifier boards replaces the thumbscrews with a clamping frame, as disclosed by Schwar, et al. In this arrangement, a ringlike frame with a hinge is raised to accept the DUT board, which is inserted between the ringlike frame and the load board. The ringlike frame also includes a latch to clamp the DUT board to the load board, with the PE boards again underlying the load board.
The two board configurations discussed above share some common problems. In both board configurations, electromechanical couplings are required between the PE boards and the load board, and between the load board and the DUT board. This double connector signal path permits, or provides, an enhanced opportunity for undesirable noise disturbances to be combined with the electrical signals channeled down the path. The intermediate position of the load board also makes for more difficult access to the underlying PE boards. Other problems are unique to each configuration.
The thumbscrew configuration uses compressible pins to maintain a selected amount of space between the two boards. When installing a DUT board on a load board, it is desirable to depress each of the compressible pins by an equal amount, achieving a uniform electrical contact between the heads of the I/O pins and their related contact points on the DUT board. However, with a plurality of thumbscrews there can be no assurance that each of the thumbscrews has been screwed into the load board to the same extent. In point of fact, the screws will generally not be uniformly tightened, causing non-uniformities in electrical contact. Some I/O pins may even fail to make contact with the DUT board, resulting in false indications of design or manufacturing errors during testing of the chip.
In addition, the use of multiple removable thumbscrews increases the risk of physical damage to the sensitive underlying electronics. For example, if an inadvertently dropped thumbscrew falls into the verifier chassis and makes contact with one or more electrical paths, a conducting bridge formed thereby could cause a damaging short circuit.
The Schwar, et al., positioning frame, although providing a better connection between a DUT board and a load board, tends to impair access to the PE boards. When the load board is removed to service the PE boards, the adjacent PE boards may be cracked or broken. Furthermore, the positioning frame configuration of Schwar, et al., provides no manipulator interface. Naturally then, direct die testing is difficult.
In summary, design verification systems generally require the careful alignment and mating of three types of electronics boards "stacked" on top of each other from top to bottom as follows: a DUT board on top, a backplane (or load board), and a plurality of underlying PE boards. Past solutions to configuring these boards have resulted in two serious disadvantages. First, signal integrity between the DUT board and the PE boards has suffered since signals have been channeled by electromechanical connectors through the intermediate signal path defined by the backplane Second, maintaining the PE boards without causing short circuits or breaking connectors has been an extraordinary achievement. Therefore, a need exists for improvements in VLSI device testers of a nature that will result in enhanced electrical signal integrity, ease of maintenance, and the ability to provide for manipulator and wafer prober interfacing.